In general, a time to digital converter (TDC) is a device for recognizing events and providing a digital representation of the time they occurred. Time-to-digital converters or also called time digitizers are commonly used to measure a time interval and convert it into a digital output. TDCs are used in many different applications, where the time interval between two signal pulses shall be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a predefined threshold.
A lot of different types of TDCs currently exist. A Vernier TDC uses two delay lines, with respective inverter delay of t1 and t2. The effective time resolution is given by the delay difference t1−t2 (assuming t1>t2). Since time resolution is determined by a very small delay difference, a very large number of inverter stages is required to cover a large detection range which leads to delay mismatch and meanwhile increases power consumption. A pulse-shrinking TDC that utilizes the difference between the rise time and the fall time of e.g., an inverter, is severely affected by process-voltage-temperature (PVT) variations. A time-amplifying TDC amplifies the time residue from a coarse TDC, which is then resolved in a fine TDC, in the same fashion as a two-step A/D converter, with the same attending linearity issue (critically dependent on PVT variations). A passive phase-interpolating TDC uses passive devices to achieve a sub-gate-delay, but its precision is limited by parasitic capacitances on the output nodes between interpolating resistors. A gated-ring oscillator TDC (GRO TDC) has the noise-shaping characteristic. The quantization noise is shaped in frequency as in a first-order ΔΣ modulator, i.e., it is largely pushed towards higher frequencies. Since the GRO TDC operates in high frequency, i.e, several Giga Hz the power consumption is very high and the 1st order noise-shaping limits its bandwidth.
There is a need to improve the accuracy of time to digital converters. In particular it is required to improve the time-to-digital converter (TDC) resolution to about 1 ps, which is an order-of-magnitude better than that provided by the delay of an inverter delay in a given process technology. This kind of TDC resolution is extremely challenging, but nowadays needed, in low-power mobile applications, such as all-digital PLL (ADPLL)-based cellular phones.